1. Field of the Invention
The present invention generally relates to receiver circuits for making compatible semiconductor devices having different voltage requirements and, more particularly, to receiver circuits which are less prone to damage from electrostatic discharge (ESD).
2. Description of the Related Art
There are a multitude of integrated semiconductor devices such as metal oxide semiconductor (MOS) memories and transistor-transistor logic (TTL) devices which are designed to operate at higher voltages, typically 5V. As technology progresses, and higher density integration is realized, individual devices are becoming smaller. These smaller devices are more prone to so called hot electron effects and other deleterious effects at higher voltages. Hence, the trend is to design modern devices to operate at lower voltages. There are many advantages to using lower voltages. Switching times are typically faster since the voltage swing between logic states is not as great. Also, lower voltage devices consume less power and therefore conserve energy and generate less heat.
In a single system, such as a computer containing a microprocessor, memory, and various peripheral chips, there may be devices and families of devices present which operate at different voltages such as, for example, 5V, 3.3V, 2.5V, and 1.8V. Therefore, data signals communicating from one device to another must first be passed through a receiver circuit in order to be made compatible.
Dielectric over-voltage is an increasing concern in mixed voltage receiver circuit applications. Referring now to FIG. 1, there is shown a simple receiver which may be used, for example, to interface 5.0 V with a 2.5 V technology, 3.3 V with a 2.5 V technology, 3.3 V with a 1.8 V technology, or perhaps 2.5 V with a 1.8 V technology. An N-channel field effect transistor (NFET) pass transistor 10 may be used to lower the voltage on the receiver dielectric to avoid electrical overstress. The addition of the NFET pass transistor provides the advantage of noise filtration for signals presented at the input pad 12. Unfortunately, the NFET pass transistor 10 also introduces a voltage drop between an input pad 12 and the receiver 14 which may degrade the signal to an undeterminable level at the inverter portion 14 of the receiver.
Referring to FIG. 2, a solution to this voltage drop is shown employing a half-latch "keeper" circuit comprising a feedback FET 16 that pulls and "keeps" the node N at the input of the inverter 14 to a full Vdd power supply voltage as long as the output of a subsequent inverter 14 remains low. In this half-latch keeper circuit, the pad 12 is connected to an NFET pass transistor 10. The NFET pass transistor 10 is followed by an inverter comprising p-channel and n-channel MOSFETs (NFET 18 and PFET 20, respectively) connected between first and second voltage supplies. The center or output node M of the inverter 14 is fed back to the gate of the PFET 16. The PFET 16 source is connected to Vdd and the drain is connected to the inverter input node N.
Unfortunately, the addition of the PFET half-latch keeper transistor 16 is susceptible to electrostatic discharge (ESD) and tends to fail at relatively low ESD levels. For example, in certain semiconductor chips where all pins are at an ESD level over 8K V, the pins employing a half-latch keeper circuit tend to fail at only 2.5K V, thus indicating that this circuit is not ESD robust.
The primary reason for this ESD failure is that when the Vdd power supply is grounded, the PFET keeper's 16 source and well (body) are also grounded. When a positive polarity ESD impulse is applied to the input pad 12, a current path is established from the input pad 12, though the NFET pass transistor 10 to the p+ diode of the PFET 16 to ground (i.e., the PFET 16 becomes forward biased). The resulting current path which is established leads to failure of the PFET 16, and the NFET pass transistor 10. This is especially a concern with technologies that have a small channel length, a mixed voltage I/O circuit, or an ESD network with a late turn-on voltage. The failure mechanism results because when the PFET 16 diode establishes a ground potential, a single pass transistor exists. In this case, MOSFET snap-back occurs followed by MOSFET secondary breakdown, leading to a low ESD tolerance and device failure.